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I need your clothes, your boots, and your motorcycle
2026-06-18 @ 08:28:04Points: 50Comments: 36
AMD silently removes memory encryption from consumer Ryzen CPUs
2026-06-18 @ 08:08:00Points: 150Comments: 72
The Forge We Deserve
2026-06-18 @ 07:46:55Points: 31Comments: 33
The Australian Government to Require SMS/MMS Sender ID Registraion
2026-06-18 @ 06:23:24Points: 106Comments: 61
DeepSeek Introduces Vision
2026-06-18 @ 06:17:40Points: 181Comments: 81
I Hate Compilers
2026-06-18 @ 05:10:28Points: 89Comments: 65
SteamOS Linux 3.8 released as stable
2026-06-18 @ 04:05:06Points: 169Comments: 55
Nim Conf 2026 (Online, Sat June 20)
2026-06-18 @ 03:38:31Points: 54Comments: 8
Local Qwen isn't a worse Opus, it's a different tool
2026-06-18 @ 03:04:20Points: 246Comments: 119
AI Compute Extensions (ACE) Specification
2026-06-18 @ 02:32:01Points: 41Comments: 17
Midjourney Medical
2026-06-18 @ 01:59:51Points: 845Comments: 578
Taxonomy of the Occlupanida (parasitoids on bread bag tags)
2026-06-17 @ 23:20:38Points: 152Comments: 38
Clojure Hosted on Go
2026-06-17 @ 23:14:49Points: 151Comments: 17
Storied Colors – A catalogue of named colors
2026-06-17 @ 21:49:03Points: 181Comments: 41
A robot is sprinting towards you. Do you want it running on Claude or Grok?
2026-06-17 @ 21:00:07Points: 253Comments: 193
Loreline – Tools for writing interactive fiction
2026-06-17 @ 20:29:15Points: 181Comments: 27
How Madrid built its metro cheaply (2024)
2026-06-17 @ 19:59:27Points: 158Comments: 102
Show HN: An 8-bit live gamecast for baseball
2026-06-17 @ 16:44:15Points: 235Comments: 121
Been waiting to share this for when there’s actually a good slate of games happening since the site is pretty bare otherwise.
Here is today's schedule:
Mets @ Reds - 9:40am PDT https://ribbie.tv/watch/game/824503
Royals @ Nationals - 10:05am PDT https://ribbie.tv/watch/game/822721
Marlins @ Phillies - 10:05am PDT https://ribbie.tv/watch/game/823450
Tigers @ Astros - 11:10am PDT https://ribbie.tv/watch/game/824178
Padres @ Cardinals - 11:15am PDT https://ribbie.tv/watch/game/823044
..and another 14 games throughout the later day.
I'm still early on in this project, but I've tried to add little details with actual stadiums, day and night modes, between inning graphics and interstitials, live scoreboards, etc.
Would love any feedback and ideas. Thanks for checking it out!
Launch HN: Adam (YC W25) – Open-Source AI CAD
2026-06-17 @ 16:14:04Points: 187Comments: 87
- AI will be the primary medium for creating mechanical designs just like it is in software today.
- The best paradigm for CAD generation is to generate CAD as code (text -> code -> CAD).
We’re building CADAM, an open source Text to CAD platform. It's a React app (TanStack Start) with a Supabase backend for auth, database, and file storage. Think of it like AI TinkerCAD.
Demo: https://www.youtube.com/watch?v=iESOr7EGWqk Try it: https://adam.new/cadam/
What it does:
- Generates parametric 3D models from natural language, with support for both text prompts and image references.
- Outputs OpenSCAD code with automatically extracted parameters that surface as interactive sliders for instant dimension tweaking
- Exports as .STL or .SCAD (plus OBJ, GLB/GLTF, FBX, and DXF)
Under the hood:
- One agentic endpoint with two modes that swap system prompts and tools: a parametric mode that writes/edits OpenSCAD via a build_parametric_model tool, and a mesh mode that generates 3D textured meshes.
- Simple parameter tweaks bypass the model entirely; adjusting a slider does a deterministic regex update on the SCAD source, requiring no LLM call.
- Model-agnostic via the Vercel AI SDK: Anthropic (Claude), Google (Gemini), and OpenAI/others through OpenRouter, with adaptive thinking auto-enabled on newer models. Surprisingly, in our evals Gemini 3.1 Pro is the top model.
- Runs fully in-browser by compiling OpenSCAD to WebAssembly (in a Web Worker, so the UI never blocks) and rendering with Three.js via React Three Fiber
- Supports BOSL, BOSL2, and MCAD libraries, plus custom font support (Geist) for text in models
Future improvements:
- Support both build123d and CadQuery. This will allow us to move beyond CSG primitives to constraint-driven modeling and provide direct comparisons to other code-as-CAD primitives.
- Better spatial context: UI for face/edge selection and viewport image integration to give LLMs spatial understanding
You can clone the repo and run it locally! Contributions are very welcome.
Volkswagen started blocking GrapheneOS users
2026-06-17 @ 15:04:47Points: 709Comments: 420
Lore – Open source version control system designed for scalability
2026-06-17 @ 14:30:27Points: 1159Comments: 614
Why thinking out loud with someone beats thinking alone
2026-06-17 @ 13:00:38Points: 282Comments: 122
RFC 10008: The new HTTP Query Method
2026-06-17 @ 10:51:17Points: 382Comments: 159
US holds off blacklisting DeepSeek, more than 100 firms deemed security risks
2026-06-17 @ 03:55:16Points: 467Comments: 516
How we run Firecracker VMs inside EC2 and start browsers in less than 1s
2026-06-16 @ 15:15:01Points: 286Comments: 178
The 2-Year Apartment Rule
2026-06-16 @ 12:00:48Points: 38Comments: 78
About ASCII art and Jgs font (2023)
2026-06-16 @ 10:51:14Points: 13Comments: 0
Show HN: We built an 8-bit CPU as 2nd year EE students
2026-06-15 @ 20:22:48Points: 80Comments: 20
key features: Custom 16-instruction Harvard ISA, 8-bit fixed format, 4 general purpose registers
Hardwired control unit built entirely from AND/OR gate logic matrix
Dual-phase clocking to eliminate race conditions
Bootstrap Control Unit that cold-boots via ROM-to-RAM transfer Early-exit conditional branching that saves upto 25% cycles when conditions aren't met
Full design specification document with version control
Since this was our first time doing such teamwork and a new thing we used RISC based system that fetches an 8-bit instruction from Instruction memory 4 bits of which translate to an instruction the last two bits are for source and destination registers. There are a total of 4 registers in the system with two memory units namely Data SRAM and I SRAM, the system follows a Harvard architecture.
There are design discrepancies too since it was our first time designing such a system and on top of that completely hardwired too.
To solve the problem of cold booting a bootloader is present too that copies the contents of a temporary ROM into instruction RAM and then hands over the reins to the CPU.
We also implemented conditional branching as well as early exit branching too that only checks for zero or carry flag and branches without wasting cycles, if the conditions are not met the Program counter increments.
Moreover we also created a complete documentation with version control describing each necessary part assuming prior knowledge.
Please take a look at it at https://github.com/c0rRupT9/STEPLA-1
For future development I want to implement a RISC CPU using FPGA's and connect it to an actual DRAM. We are also selling the full spec document and Logisim files for $5 to fund our passion https://tcfdiq.gumroad.com/l/zyyux Thankyou!